Referring to FIG. 6, the method for manufacturing a semiconductor device of this type is explained in the sequence of manufacturing steps.
Referring first to FIG. 6A, a device separation area 2 is selectively formed on a semiconductor substrate 1 of silicon (Si) and an N-well region 3 is then formed by ion implantation of phosphorus (P). A gate oxide film 4 and a gate electrode 5 of polysilicon are formed, and a sidewall 6 of an oxide film is formed, on a sidewall of a gate electrode 5. BF.sub.2 ions are then implanted by ion-implanation with, for example, an acceleration energy of 20 keV and a dosage of 3E15 (3.times.10.sup.15)cm.sup.-2, followed by heat treatment under the conditions of, for example, 1000.degree. C. and 10 seconds in a nitrogen atmosphere for activation to form a p-type source drain region 7.
Then, as shown in FIG. 6B, arsenic (As) is implanted by ion implantation under the conditions of, for example, 30 keV and 3E14 cm.sup.-2 to render the surface of the p-type source-drain region 7 and the gate electrode 5 amorphous.
Then, as shown in FIG. 6C, titanium (Ti) is deposited by a sputtering method, followed by heat treatment of, for example, 700.degree. C. for 30 seconds, to form titanium silicide layer 9 on at least the p-type source-drain region 7 and the gate electrode 5. Non-reacted titanium is then removed using a solution obtained on mixing ammonia, hydrogen peroxide and water at a ratio of ammonia: hydrogen peroxide: water of 1:1:5, followed by heat treatment at 800.degree. C. for 10 seconds to lower the resistance of the titanium silicide layer 9.
At this time, titanium silicide layer is not formed in the device separation region 2 of the oxide film nor on the surface of the sidewall 6. In fact, a layer-to-layer insulating film is then formed followed by opening of contact holes and formation of interconnections. These steps, however, are irrelevant to the subject-matter of the present invention and hence are not stated here specifically.
With the above-described conventional manufacturing method, boron (B) contained in the p-type impurity diffusion layer is sucked up by (diffuses into) the titanium silicide layer 9 of a lower concentration during the time the titanium silicide layer 9 is formed on the semiconductor substrate 1, thus lowering the boron concentration on the surface of the p-type impurity diffusion layer.
The result is that the contact resistance between the titanium silicide layer 9 and the p-type impurity layer is increased to lower the current driving capability of the p-type MOS transistor.
As a conventional method for overcoming this inconvenience, there is proposed in e.g., JP Patent Kokai Publication JP-A-4-150019 a manufacturing method in which the boron concentration at an interface between the p-type impurity diffusion layer and the titanium silicide layer is prohibited from being lowered despite formation of the titanium silicide layer for suppressing the contact resistance between the two layers.
FIGS. 7A to 7C show the conventional manufacturing method step-by-step. Referring first to FIG. 7A, a device separation region 2 is formed on a semiconductor substrate 1 mainly composed of silicon. Then, after formation of an N well area 3, boron is implanted by ion implantation into the semiconductor substrate 1 and activated to form a ptype source-drain region 7 near the surface of the semiconductor substrate 1.
Then as shown in FIG. 7B, titanium ions are implanted at an implantation energy of 30 keV and a dosage of 1E17 cm.sup.-2, using TiCl.sub.4 as an ion source, to implant titanium ions near the surface of the p-type source-drain region 7.
If titanium ions are implanted in this manner, titanium ions exist between silicon atoms with a content of the p-type impurities. In this state, boron is further ion-implanted at an implantation energy of 20 keV and a dosage of about 1E15 cm.sup.-2.
Then, thermal annealing is carried out by a lamp annealing method at a level of 400 to 900.degree. C. This leads to reaction between titanium and silicon in a portion of the semiconductor substrate to form titanium silicide 9, as shown in FIG. 7C.
On the other hand, titanium silicide is not formed on the oxide film of the device separation region etc. In the process in which titanium is reacted with silicon to titanium silicide, boron in titanium silicide is diffused to outside. Since the silicide layer is approximately 50 nm, whilst the peak of boron concentration is approximately 60 nm in depth. Thus, even if boron in the titanium silicide layer is diffused, the concentration of boron in titanium silicide and silicon is extremely high, so that, even under certain diffusion of boron into titanium silicide by heat application in the subsequent process, the boron concentration in the interface between silicon and titanium silicide is not lowered. Thus, the contact resistance between the titanium silicide layer and p-type impurity diffusion layer can be prohibited from being increased.